This invention relates to circuitry for applying reading, programming and erasing voltages to wordlines of floating-gate-type, electrically-erasable-programmable-memory (EEPROM) arrays and to the control gates of the individual memory cells attached to those wordlines.
This application discloses and claims circuitry that is an improvement over the wordline driver circuitry described in U.S. Pat. No. 4,823,318, issued Apr. 18, 1989 and also assigned to Texas Instruments Incorporated.
EEPROM arrays of the type used with the circuitry of this application are described, for example, in co-pending U.S. Pat. applications No. 07/274,718 (a continuation of U.S. Pat. application No. 07/056,196, now abandoned); No 07219,528; No. 07/219,529 and No. 07/219,530; each of those applications being also assigned to Texas Instruments Incorporated. EEPROM arrays of the type described in the foregoing applications require circuitry that will switch as many as four different values of voltage to each wordline for the purposes of reading, programming and erasing information stored on the floating gates. One of those voltages, the erasing voltage, must be negative with respect to the bitlines or source-drain regions.
During read operation of EEPROM cells of the floating-gate type, a voltage Vsv of perhaps +3 volts above reference potential is applied to the wordline and control gate of the selected cell, with the source connected to reference potential Vss, which may be the circuit ground, and with the drain connected to a read voltage of perhaps +1.5 volts above reference potential. Non-selected wordlines are usually tied to reference potential Vss.
During programming operation of such EEPROM cells, a voltage Vpp of perhaps +12 to +16 volts above reference potential is applied to the wordline and control gate of the selected cell, with the source of the selected cell at reference potential Vss and with the drain of the selected cell either allowed to float or tied to a low voltage or reference potential Vss. The programming voltage Vpp is typically applied for a period of 10 milliseconds and produces a shift in voltage threshold of approximately 4.5 volts or more. Non-selected wordlines may be connected to reference potential Vss or, to prevent disturb on non-selected cells, the non-selected wordlines may be connected to a voltage of perhaps +6 to +8 volts above reference potential Vss.
During erasing operation of such EEPROM cells, a voltage Ver of perhaps -10 to -12 volts below reference potential Vss is applied to the wordline and control gate of the selected cell or, in the cases of a so-called "flash-erase" type of EEPROMs, to all of the wordlines and control gates with the sources of the erased cells being at perhaps +4 to +6 volts above reference potential Vss and with the drains allowed to float or tied to a low voltage or reference potential Vss. The erasing voltages are typically applied for a period of 10 milliseconds and produce a voltage threshold of approximately one volt. The non-selected wordlines are usually tied to reference potential Vss during erasure.
The various EEPROM wordline voltages may be generated from the approximately +5 volt external supply voltage Vdd using charge-pump capacitors located on the memory chip. Circuits for switching from one voltage to a second voltage are well-known. For example, such circuits are used to change the bitline voltages from one value to another value when changing from the programming mode of operation to the erasing mode of operation. Such circuits for switching between a positive read voltage, a positive programming voltage, and a reference voltage are known in the prior art pertaining to electrically-programmable-read-only-memories (EPROMs). However, in the case of EEPROMs, there is a need for improved circuits that will not only switch wordline reading and programming voltages, but which will also switch negative erasing voltages to the selected wordline. Switching of negative voltages presents a unique problem in that such circuits must be designed to prevent P-N junctions between the diffused areas and the substrate of such integrated circuits from becoming forward biased during application of negative erase voltages.
In addition, there is a need for circuitry that will supply a third value of positive voltage to non-selected wordlines during programming operation and to thereby lessen the probability that non-selected memory cells will be disturbed.